LAB #3

IMPLEMENTATION WITH ONE GATE TYPE

• Prelab Assignment
  • ...

• Integrated Circuits
  • 7400: Quadruple 2-Input Positive NAND Gates
  • 7410: Triple 3-Input Positive NAND Gates
  • 7420: Dual 4-Input Positive NAND Gates

• Laboratory Experiments
  1. Design and build an even parity generator for a 3-bit word. This circuit will have three inputs ( the 3 bits of the word ) and one output. Output should be a 1 if there is an odd number of 1's in the input word; otherwise the output should be 0 (if there is an even number of 1's in the input word). Construct the circuit with nothing but NAND gates.
     1. Construct the truth table for the even parity generator.

     2. Give an SOP equation for the truth table.

     3. Give a POS equation for the truth table.

     4. Construct a two-level AND-OR network.

     5. Construct a two-level NAND-NAND network.

     6. Construct a two-level OR-AND network.

     7. Construct a two-level NOR-NOR network.