LAB #4

EXPRESSION REDUCTION TECHNIQUES

• Prelab Assignment
  • ...

• Integrated Circuits
  • 7400: Quadruple 2-Input Positive NAND Gates

  • 7404: Hex Inverters

  • 7410: Triple 3-Input Positive NAND Gates

• Laboratory Experiments
  1. Design a circuit that given a 4-bit BCD digit (0-9) will produce a 2-bit quotient and 2-bit remainder for a division by 3. The circuit will have four inputs, the 4-bits of the BCD digit and four outputs, 2-bits for the quotient and 2-bits for the remainder.
     1. Construct the truth table for the previous circuit.

     2. Give an SOP equation for the truth table.

     3. Construct a K-Map for Q1.

     4. Construct a K-Map for Q2.

     5. Construct a K-Map for R1.

     6. Construct a K-Map for R2.

     7. Construct a two-level AND-OR network.

     8. Construct a two-level NAND-NAND network.

     9. Wire and test your NAND-NAND network.

     10. Have instructor verify your circuit.