LAB #7

LATCHES AND FLIP-FLOPS

• Prelab Assignment
  • ...

• Integrated Circuits
  • 7402: Quadruple 2-Input Positive NOR Gates

  • 7476: Dual JK Flip-Flops with Preset and Clear

  • 7474: Dual D-Type Positive-Edge-Triggered Flip-Flops with Preset and Clear

• Laboratory Experiments
  1. Wire the basic NOR implementation of the SR latch as shown:
     1. Use s input to set the flip-flop

     2. Set both S and R to 1. What happens and why?

     3. Return S and R to 0 'simultaneously'. Repeat b.) and c.) several times. Do the outputs return to the same state each time S and R are returned to 0?

  2. Connect the JK inputs of a 7476 JK flip-flop to the input switches on the D/A trainer. Connect the clock input of the flip-flop to one of the pulser switches and the outputs of the flip-flop to an LED.
     1. Verify proper operation by trying each JK combination and pressing the pulser to clock the flip-flop. Note that changing the JK inpus does not affect the state of teh flip-flop until the flip-flop is clocked.

     2. When does the flip-flop change state? On a rising or falling edge of the clock?

     3. Connect the clock input to S3 on the D/A trainer and observe switch bounce. Set J=K=1, clock the flip-flop by switching S3 and explain your results?

     4. Produce a timing diagram showing the clock input, the JK inputs, and the outputs as the sequence in (a) is performed.